In power management applications, co-packaging an integrated circuit with a discrete semiconductor device such as a discrete power device of metal oxide semiconductor field effect transistor (“MOSFET”), junction field effect transistor (“JFET”), or other devices has become a major trend for cost and size saving. In most high voltage and/or large current power management applications, a vertical discrete transistor such as a vertical power transistor of vertical MOSFET, vertical JFET or field effect transistor (“FET”) with integrated Schottky diode is often used and co-packaged with its integrated control circuit to achieve high power management performance while reducing cost and package size.
Conventionally, a semiconductor die of vertical power MOSFET, JFET, FET with an integrated Schottky diode or other vertical transistors typically comprise a drain/cathode electrode on a bottom surface and source and gate electrodes on a top surface. In many power management applications, an N-type vertical transistor is configured as a low-side switch, meaning that the source electrode is connected to the lowest potential (i.e. ground) and an electrical load is connected between the drain electrode and a higher potential (i.e. VDD). When the MOSFET is switched on and off (by modulation of the gate-source voltage), the source voltage stays relatively constant, while the drain voltage alternates between high and low voltages. Since the drain electrode is on the bottom surface of the MOSFET die, it is typically connected to the leadframe of a package. For high-power devices, the leadframe is exposed for better thermal performance. The presence of high and transitioning voltage on the exposed leadframe is often undesirable because it requires electrical isolation and can be a source of radiated electromagnetic interference (“EMI”).
Prior art co-package solutions (i.e., a control chip and a vertical MOSFET in the same package) use vertical MOSFET devices that have backside drain. The high and transient voltage on the drain causes isolation and EMI problems as described above. Moreover, since the MOSFET drain is at a different voltage than the substrate of the control chip, they may not be electrically connected to the same leadframe. One prior art solution uses a non-conductive epoxy to attach the control chip to the leadframe. This provides the needed isolation, but compromises the thermal performance (i.e., the ability of the package to dissipate heat produced in the control chip). Another approach uses a special package with a split leadframe, one piece under the control chip and a separate (and isolated) piece under the MOSFET. This increases packaging cost and can complicate the attachment of the package to a print circuit (“PC”) board.